The ever-increasing capacity of small form factor memory cards allows for new possibilities in storing and distributing digital content. Content stored on commercially available cards such as MultiMedia cards (MMC) and Secure Digital (SD) cards may be accessed by a variety of host devices. The organizations that define standards for small form factor memory cards may define a limit for the maximum instantaneous or average power that a memory card may consume. These limits are necessary so that manufacturers of host devices such as cellular telephones may budget the instantaneous or average power necessary for memory card access operations, and are necessary in order to maintain interoperability with future and legacy host devices.
As the storage capacity and complexity of small form factor memory cards increases, the instantaneous or average power potentially consumed by these devices also could increase, particularly during power-intensive operations such as reset, programming, writing, or erase operations. For example, small form factor memory cards typically contain multiple NAND non-volatile memory dies. An operation such as a power-on reset (POR) typically involves resetting several NAND dies in parallel, or approximately at the same time, such as by transmitting a reset command to all of the NAND dies associated with a chip enable signal. Initializing several dies at about the same time may cause a significant amount of combined inrush current, which may exceed an instantaneous power consumption limit, or a maximum permissible power consumption over a defined period of time.
One design approach to achieving power compliance while resetting a large number of non-volatile memories includes a Power-on Read Disable (PRDIS) memory input control, which disables each memory die from initiating its own power-on reset when power is applied to the memory card. This avoids resetting all of the memory dies at the same time as other circuitry on the memory card is reset. However, large numbers of the memory dies are still reset in parallel by the memory card controller after the controller completes initialization. Therefore, PRDIS control is not a viable solution when the current requirements solely for resetting the non-volatile memories in parallel already exceeds a maximum limit established by the standard applicable to a particular small form factor memory card.
Another solution for avoiding large inrush current during power-on of a small form factor memory cards includes staggering the times when each die associated with a common chip enable (CE) line starts initialization. This delay, however, is typically a fixed time that is not programmable. There are limitations to the duration of delays that may be implemented using this approach, and to the ordering of the die initialization that may be achieved using this approach. Therefore, a system that utilizes hard-wired or fixed delays limits the possible configurations that can be used, and requires custom circuitry for each implementation.